The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Mar. 17, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Andreas Stahl, Munich, DE;

Hubert Martin Bode, Haar, DE;

Ilhan Hatirnaz, Munich, DE;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H03K 19/00 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H03K 19/003 (2006.01); H03K 19/21 (2006.01); H03K 19/173 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); H01L 21/3213 (2013.01); H01L 21/823871 (2013.01); H01L 23/53271 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H03K 19/00315 (2013.01); H03K 19/00392 (2013.01); H03K 19/1735 (2013.01); H03K 19/17764 (2013.01); H03K 19/215 (2013.01); H01L 2027/11835 (2013.01); H01L 2027/11866 (2013.01); H01L 2027/11875 (2013.01);
Abstract

The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.


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