The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Mar. 16, 2016
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Jun Zhao, Fremont, CA (US);

Brandon Day, Seattle, WA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); G05F 1/10 (2006.01); H02M 3/156 (2006.01); H02M 1/088 (2006.01); G05F 1/56 (2006.01); G05F 1/563 (2006.01); H03F 1/02 (2006.01); H02M 3/155 (2006.01);
U.S. Cl.
CPC ...
H02M 1/088 (2013.01); G05F 1/56 (2013.01); G05F 1/563 (2013.01); H02M 3/155 (2013.01); H03F 1/0261 (2013.01); H02M 2001/0045 (2013.01);
Abstract

Apparatus and methods for a bias supply circuit to support power supply including a switched-mode voltage converter cascaded with an n-channel-based linear regulator are provided. In an example, a cascaded power supply system can include a switched-mode DC-to-DC power converter, including an input voltage node, a first stage output voltage node, and a bootstrapped floating bias voltage node, and a linear regulator circuit. The linear regulator circuit can include an n-channel field-effect transistor (NFET) pass transistor, including a drain terminal coupled to the first stage output voltage node, a gate terminal, and a source terminal configured to provide a second-stage output voltage, and a gate driver circuit, including a driver output coupled to the gate terminal of the NFET pass transistor, and a high side supply node configured to receive a bias voltage generated from the bootstrapped floating bias voltage node.


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