The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Sep. 28, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Jung Chen, Hsinchu County, TW;

Tzu-Ping Chen, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); H01L 27/11524 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7887 (2013.01); G11C 16/0408 (2013.01); G11C 16/0416 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11524 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.


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