The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Feb. 27, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Katsuhisa Tanaka, Arakawa, JP;

Ryosuke Iijima, Setagaya, JP;

Shinya Kyogoku, Tsukuba, JP;

Shinsuke Harada, Tsukuba, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/16 (2006.01); H01L 21/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 29/1608 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 21/046 (2013.01); H01L 21/049 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a first conductive portion, a semiconductor portion including silicon carbide, and a first insulating portion. The semiconductor portion includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is provided between the second partial region and the second semiconductor region. The fourth semiconductor region is provided between the first conductive portion and the first partial region. The first insulating portion includes first to third portions. A portion of the first portion is positioned between the first conductive portion and the fourth semiconductor region. The second portion is positioned between the second semiconductor region and the portion of the first conductive portion and between the first conductive portion and the third semiconductor region. The third portion is provided between the first and second portions. The third portion has first and second surfaces.


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