The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Jun. 16, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Chenglong Zhang, Shanghai, CN;

Erhu Zheng, Shanghai, CN;

Haiyang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 23/535 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 23/485 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76819 (2013.01); H01L 23/485 (2013.01); H01L 23/535 (2013.01); H01L 27/11521 (2013.01); H01L 29/42324 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); H01L 21/76834 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.


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