The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2019

Filed:

Nov. 09, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bruce Querbach, Hillsboro, OR (US);

Pete D. Vogt, Boulder, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 5/06 (2006.01); G06F 1/18 (2006.01); H01R 12/71 (2011.01); H05K 1/18 (2006.01); G11C 5/04 (2006.01); H05K 1/14 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G06F 1/18 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 5/066 (2013.01); H01R 12/716 (2013.01); H05K 1/141 (2013.01); H05K 1/181 (2013.01); H05K 1/0295 (2013.01); H05K 2201/09409 (2013.01); H05K 2201/10159 (2013.01);
Abstract

Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.


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