The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2019
Filed:
Nov. 27, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Vinu K. Elias, Austin, TX (US);
Sundar Ramani, Bangalore, IN;
Arvind S. Tomar, San Jose, CA (US);
Jianjun Liu, Shanghai, CN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/3212 (2019.01); H03K 19/0185 (2006.01); G06F 1/3234 (2019.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3212 (2013.01); G06F 1/3234 (2013.01); H03K 19/018585 (2013.01); H03K 19/018592 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 2207/105 (2013.01);
Abstract
In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.