The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Jul. 26, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Didier Salle, Toulouse, FR;

Olivier Vincent Doare, La Salvetat St Gilles, FR;

Birama Goumballa, Larra, FR;

Cristian Pavao Moreira, Frouzins, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/099 (2006.01); H03K 4/06 (2006.01); H03L 7/085 (2006.01); G01S 13/34 (2006.01); H03C 3/09 (2006.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01); H03L 7/16 (2006.01); G01S 7/35 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0992 (2013.01); G01S 13/343 (2013.01); H03C 3/0908 (2013.01); H03K 4/06 (2013.01); H03L 7/08 (2013.01); H03L 7/085 (2013.01); H03L 7/093 (2013.01); H03L 7/16 (2013.01); G01S 7/35 (2013.01); H03L 2207/50 (2013.01);
Abstract

A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.


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