The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Dec. 28, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Satyanarayana Sahu, San Diego, CA (US);

Xiangdong Chen, San Diego, CA (US);

Venugopal Boynapalli, San Marcos, CA (US);

Hyeokjin Lim, San Diego, CA (US);

Mickael Malabry, San Diego, CA (US);

Mukul Gupta, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H03K 19/0948 (2006.01); H01L 27/118 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 27/0924 (2013.01); H01L 2027/11853 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11887 (2013.01); H01L 2027/11888 (2013.01);
Abstract

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mlayer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mlayer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mlayer interconnects are parallel. The MOS device further includes a first Mlayer interconnect extending in a second direction orthogonal to the first direction. The first Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The MOS device further includes a second Mlayer interconnect extending in the second direction. The second Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The second Mlayer interconnect is parallel to the first Mlayer interconnect.


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