The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Feb. 13, 2017
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Robert L. Bruce, White Plains, NY (US);
Gregory M. Fritz, Wakefield, MA (US);
Eric A. Joseph, White Plains, NY (US);
Hiroyuki Miyazoe, White Plains, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01); H01L 21/288 (2006.01); H01L 21/3213 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/2855 (2013.01); H01L 21/2885 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H01L 21/32133 (2013.01); H01L 21/7685 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76838 (2013.01); H01L 21/76841 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 21/76892 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53252 (2013.01); H01L 24/05 (2013.01); H01L 21/76852 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01);
Abstract
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.