The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Mar. 14, 2013
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;
Inventors:
Su Yeon Doo, Seoul, KR;
Seungjun Bae, Hwaseong-si, KR;
Sihong Kim, Yongin-si, KR;
Hosung Song, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/18 (2006.01); G11C 5/04 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G06F 11/10 (2006.01); G11C 8/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G06F 11/1004 (2013.01); G11C 5/04 (2013.01); G11C 7/22 (2013.01); G11C 11/4076 (2013.01); G11C 2029/0411 (2013.01);
Abstract
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.