The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Mar. 27, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Aswin Ramakrishnan, El Cerrito, CA (US);
Jalal Wehbeh, Sunnyvale, CA (US);
Robert MacDonald, Austin, TX (US);
Federico Politi, Menlo Park, CA (US);
Ajish Thomas, San Jose, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components. When a second input stimulus vector is associated with a second delay arc that is equivalent to the first delay arc in the logic path, the method includes selecting one of the first or second input stimulus vectors for a set of input stimuli vectors. The method further includes determining an electromigration effect on the partition netlist with the input stimuli vectors.