The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Dec. 21, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Philippe Thierry, Meudon, FR;

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); H04L 12/911 (2013.01);
U.S. Cl.
CPC ...
H04L 67/32 (2013.01); H04L 47/70 (2013.01); H04L 67/1004 (2013.01);
Abstract

Systems and methods for scheduling highly-parallel applications executed by high-performance computing systems. An example processing system may comprise: a control register and a processing core, communicatively coupled to the control register. The processing core may be configured to receive a node allocation request specifying an expected running time of an application and a requested number of nodes of a cluster of nodes; determine, in view of the node allocation request and a current load on the plurality of nodes, an actual number of nodes to be allocated to the application, wherein the actual number of nodes to be allocated to the application optimizes a cluster load criterion; and notify, using the control register, the application of the actual number of nodes.


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