The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Dec. 20, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Thomas D. Lovett, Portland, OR (US);

Albert Cheng, Bellevue, WA (US);

Mark S. Birrittella, Chippewa Falls, WI (US);

James Kunz, Plymouth, MN (US);

Todd Rimmer, Exton, PA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/933 (2013.01); H04L 12/911 (2013.01); H04L 1/00 (2006.01); H04L 12/851 (2013.01); H04L 12/805 (2013.01); H04L 12/863 (2013.01); H04L 12/865 (2013.01); H04L 1/12 (2006.01); H04L 25/14 (2006.01);
U.S. Cl.
CPC ...
H04L 47/821 (2013.01); H04L 1/0041 (2013.01); H04L 1/0061 (2013.01); H04L 1/0071 (2013.01); H04L 1/12 (2013.01); H04L 25/14 (2013.01); H04L 47/2441 (2013.01); H04L 47/365 (2013.01); H04L 47/621 (2013.01); H04L 47/6275 (2013.01);
Abstract

Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.


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