The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2019
Filed:
Sep. 16, 2016
Xilinx, Inc., San Jose, CA (US);
Ilya K. Ganusov, San Jose, CA (US);
Benjamin S. Devlin, New York, NY (US);
XILINX, INC., San Jose, CA (US);
Abstract
Aspects of various embodiments of the present disclosure are directed to methods and circuits preventing hold violations in clock synchronized circuits. In an example implementation, a circuit includes a logic circuit having a set of inputs. Signal propagation time on a signal path to at least one of the set of inputs presents a hold violation. The circuit includes first and second level-sensitive latches. The first level-sensitive latch has an output connected to the one of the plurality of inputs. The second level-sensitive latch has an input connected to an output of the logic circuit. A latch control circuit is configured to remove the hold violation on the input by providing a pulsed clock signal to a clock input of the second level-sensitive latch and an inversion of the pulsed clock signal to a clock input of the first level-sensitive latch.