The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

May. 12, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Xuewen He, Suzhou, CN;

Xiaoxiang Geng, Suzhou, CN;

Lei Zhang, Suzhou, CN;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G06F 11/18 (2006.01); G06F 11/20 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G06F 11/0793 (2013.01); G06F 11/1064 (2013.01); G06F 11/1666 (2013.01); G06F 11/18 (2013.01); G06F 11/181 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/76 (2013.01); G11C 29/789 (2013.01); G11C 29/808 (2013.01); G11C 29/846 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/1208 (2013.01); G11C 2029/4402 (2013.01);
Abstract

An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.


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