The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
Dec. 13, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Sleiman Bou-Sleiman, Chandler, AZ (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/14 (2006.01); H04L 7/033 (2006.01); H03L 7/00 (2006.01); H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); H03L 7/00 (2013.01); H03L 7/143 (2013.01); H04L 43/16 (2013.01);
Abstract
Methods, apparatuses, and systems are described related a data receiver circuit having a pair of offset edge samplers to sample a data signal, at an edge sampling time between data samples, with respect to different reference levels. A clock-data recovery (CDR) circuit of the receiver circuit may determine an A-count that corresponds to a number of times the signal level of the data signal at the edge sampling time is between the reference levels of the offset edge samples to provide a signal integrity metric for the receiver circuit. The CDR circuit may dynamically update its settings based on the A-count.