The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Feb. 02, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Hans Weber, Bayerisch Gmain, DE;

Christian Fachmann, Fuernitz, AT;

Daniel Tutuc, St. Niklas an der Drau, AT;

Andreas Voerckel, Finkenstein, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/027 (2006.01); H01L 21/308 (2006.01); H01L 21/321 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/0274 (2013.01); H01L 21/3081 (2013.01); H01L 21/3212 (2013.01); H01L 22/12 (2013.01); H01L 23/544 (2013.01); H01L 29/4236 (2013.01); H01L 29/6634 (2013.01); H01L 29/66348 (2013.01); H01L 29/66666 (2013.01); H01L 29/7397 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 29/861 (2013.01); H01L 29/7396 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract

According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.


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