The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Dec. 13, 2016
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Barry Wynne, Glossop, GB;

Mark Andrzej Gajda, Hazel Grove, GB;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/24 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01); H01L 29/161 (2006.01); H01L 29/778 (2006.01); H03K 17/0814 (2006.01); H03K 17/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 24/48 (2013.01); H01L 28/20 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/20 (2013.01); H01L 29/2003 (2013.01); H01L 29/24 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H03K 17/0814 (2013.01); H03K 17/102 (2013.01); H03K 17/107 (2013.01); H01L 2224/48137 (2013.01); H01L 2924/00014 (2013.01);
Abstract

A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.


Find Patent Forward Citations

Loading…