The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jun. 16, 2017
Applicant:

J-devices Corporation, Usuki, Oita, JP;

Inventors:

Hirokazu Machida, Sakai, JP;

Kazuhiko Kitano, Sakai, JP;

Assignee:

J-DEVICES CORPORATION, Usuki, Oita, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/544 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/142 (2013.01); H01L 21/4803 (2013.01); H01L 21/4846 (2013.01); H01L 21/4871 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 23/544 (2013.01); H01L 23/552 (2013.01); H01L 24/03 (2013.01); H01L 24/04 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 23/49816 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/03914 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/11013 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82039 (2013.01); H01L 2224/83132 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01);
Abstract

A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.


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