The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jun. 14, 2016
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

Walter Parmon, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/14 (2006.01); H05K 3/34 (2006.01); H01L 23/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/12 (2013.01); H05K 1/141 (2013.01); H05K 3/3436 (2013.01); H05K 2201/0723 (2013.01); H05K 2201/10378 (2013.01);
Abstract

Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.


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