The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
Nov. 23, 2011
Douglas Keil, West Linn, OR (US);
Edward Augustyniak, Tualatin, OR (US);
Karl Leeser, Lake Oswego, OR (US);
Mohamed Sabri, Beaverton, OR (US);
Douglas Keil, West Linn, OR (US);
Edward Augustyniak, Tualatin, OR (US);
Karl Leeser, Lake Oswego, OR (US);
Mohamed Sabri, Beaverton, OR (US);
NOVELLUS SYSTEMS, INC., Fremont, CA (US);
Abstract
A system for reducing parasitic plasma in a semiconductor process comprises a first surface and a plurality of dielectric layers that are arranged between an electrode and the first surface. The first surface and the electrode have substantially different electrical potentials. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.