The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jan. 03, 2018
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wen-Hao Ching, Zhubei, TW;

Shih-Chen Wang, Taipei, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); H03K 19/088 (2006.01); H01L 27/11541 (2017.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 16/12 (2006.01); G11C 16/04 (2006.01); H01L 27/11558 (2017.01); H01L 29/423 (2006.01); G11C 16/26 (2006.01); H01L 27/11524 (2017.01); G11C 16/34 (2006.01); H01L 29/78 (2006.01); H03K 17/082 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 7/04 (2013.01); G11C 7/109 (2013.01); G11C 7/1084 (2013.01); G11C 16/0433 (2013.01); G11C 16/0441 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 16/3472 (2013.01); H01L 27/11524 (2013.01); H01L 27/11541 (2013.01); H01L 27/11558 (2013.01); H01L 29/42328 (2013.01); H01L 29/7841 (2013.01); H03K 19/088 (2013.01); H01L 29/42364 (2013.01); H01L 29/7883 (2013.01); H03K 17/0828 (2013.01);
Abstract

A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.


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