The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jan. 26, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Perry Pelley, Austin, TX (US);

Anirban Roy, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/44 (2006.01); G11C 11/4096 (2006.01); G11C 11/16 (2006.01); G11C 7/12 (2006.01); G11C 11/4099 (2006.01); G11C 7/14 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 11/1673 (2013.01); G11C 11/4099 (2013.01);
Abstract

A semiconductor device includes an array of memory cells, and a reference voltage generation circuit including a first set of reference memory cells coupled to a first bit line, a second set of reference memory cells coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier that provides reference voltage used by sense amplifiers, and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage.


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