The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
Dec. 23, 2016
Intel Corporation, Santa Clara, CA (US);
Tat Hin Tan, Bayan Lepas, MY;
William Walter Fergusson, Sunnyvale, CA (US);
Chieu Fung Tan, Bukit Mertajam, MY;
Intel Corporation, Santa Clara, CA (US);
Abstract
A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications. To compute the resistance targets, the circuit design tools may identify critical transistors, run single-pass and DC operating point simulation to determine initial resistance values for the critical transistors, simplify parallel resistive networks, perform sensitivity analysis on the simplified networks, and perform interpolation among multiple resistive values to obtain resistive design targets meet the original RF performance specifications.