The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Sep. 29, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Yung-Hao Lin, Jhunan Township, TW;

Shin-Cheng Lin, Tainan, TW;

Hsin-Chih Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01);
Abstract

The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first III-V compound layer disposed over a substrate and a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in the interface between the first III-V compound layer and the second III-V compound layer. The semiconductor device also includes a third III-V compound layer disposed over the second III-V compound layer and a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer. The semiconductor device includes a gate structure and S/D regions disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the S/D regions.


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