The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Oct. 26, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Yinjie Ding, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Shyue Seng Tan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/405 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A method of forming a bulk transistor integrated with silicon-on-insulator (SOI) field plates, and related device, are provided. Embodiments include forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide; forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type formed between shallow trench isolation (STI) region of the p-type substrate; forming an n-drift region in the high-voltage p-type well; forming a first gate on the high-voltage p-type well; and implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region.


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