The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Nov. 22, 2017
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Ling Chiang, Hsinchu, TW;

Chun-Min Cheng, Hsinchu, TW;

Ming-Tsung Wu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/105 (2006.01); H01L 27/11597 (2017.01); H01L 27/11582 (2017.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02063 (2013.01); H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 21/02271 (2013.01); H01L 27/105 (2013.01); H01L 27/11597 (2013.01);
Abstract

A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i≥2.


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