The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

May. 25, 2017
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Kazuaki Takesako, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/7687 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01);
Abstract

A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.


Find Patent Forward Citations

Takesako, Kazuaki. (2019). Dynamic random access memory and method of manufacturing the same (U.S. Patent No. 10217748). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10217748

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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