The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Oct. 26, 2017
Applicant:

National Technology & Engineering Solutions of Sandia, Llc, Albuquerque, NM (US);

Inventors:

Randy J. Shul, Albuquerque, NM (US);

Jeffry J. Sniegowski, Tijeras, NM (US);

Kurt W. Larson, Cedar Crest, NM (US);

William A. Zortman, Corrales, NM (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); G06F 17/50 (2006.01); H01L 21/311 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 21/475 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G06F 17/50 (2013.01); H01L 21/31144 (2013.01); H01L 21/475 (2013.01); H01L 21/486 (2013.01); H01L 21/76805 (2013.01); H01L 21/76898 (2013.01); H01L 23/49827 (2013.01);
Abstract

Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.


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