The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2019
Filed:
Jan. 03, 2017
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Parag Upadhyaya, Los Gatos, CA (US);
Jing Jing, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H03B 5/12 (2006.01); H01L 23/64 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/645 (2013.01); H01L 28/10 (2013.01); H01L 29/402 (2013.01); H03B 5/1215 (2013.01); H03B 2201/0208 (2013.01);
Abstract
An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.