The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Dec. 18, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Werner Hein, Neubiberg, DE;

John Oakley, Bastrop, TX (US);

Naveen Kumar Narala, Unterhaching, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01);
Abstract

Time-critical actions of peripherals sharing a synchronous serial bus can be coordinated flexibly in real time by transmitting the messages through the bus well in advance of the scheduled execution time rather than 'just in time.' The messages include an action code addressed to the peripheral's shadow register and a time-to-strobe, measured in bus-clock cycles, calculated by a time protocol engine in the system controller and addressed to the peripheral's counting register. The action code is stored in the shadow register while the counting register counts up or down to the time-to-strobe using the bus-clock signal. When the count reaches zero, the action code is written to the function-control register, triggering immediate execution of the action. Because the time-to-strobe can be any number of clock cycles within the counting register's capacity, the transmission timing is decoupled from the execution timing, relaxing transmission-timing constraints.


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