The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Nov. 29, 2016
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Mohammad Nizam Kabir, Tempe, AZ (US);

Mariam Hoseini, San Mateo, CA (US);

Rakesh Shiwale, Chandler, AZ (US);

Doug Garrity, Gilbert, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/15 (2006.01); H03L 7/18 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15066 (2013.01); H03L 7/18 (2013.01);
Abstract

Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.


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