The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Jan. 16, 2017
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventor:

Yeong-Sheng Lee, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03D 13/00 (2006.01); H03K 5/134 (2014.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01); H03L 7/085 (2006.01); H03L 7/087 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03K 5/134 (2014.07); H03D 13/003 (2013.01); H03K 17/6872 (2013.01); H03K 19/20 (2013.01); H03L 7/085 (2013.01); H03L 7/087 (2013.01); H03K 2005/00039 (2013.01); H03K 2005/00052 (2013.01); H03K 2005/00078 (2013.01); H04L 7/033 (2013.01);
Abstract

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.


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