The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Dec. 26, 2014
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Meng Zhao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/30608 (2013.01); H01L 29/0657 (2013.01); H01L 29/0688 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66545 (2013.01); H01L 29/7842 (2013.01); H01L 21/02433 (2013.01); H01L 29/6659 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device.


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