The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Aug. 10, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Pascal Peyrot, Frouzins, FR;

Olivier Lembeye, Saint Lys, FR;

Sai Sunil Mangaonkar, Chandler, CA (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/66 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 1/02 (2006.01); H03F 3/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/642 (2013.01); H01L 24/49 (2013.01); H03F 1/0205 (2013.01); H03F 1/565 (2013.01); H03F 3/195 (2013.01); H03F 3/604 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6655 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/30107 (2013.01); H01L 2924/30111 (2013.01); H03F 2200/222 (2013.01); H03F 2200/267 (2013.01); H03F 2200/451 (2013.01);
Abstract

A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.


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