The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2019
Filed:
Dec. 23, 2015
Intel Corporation, Santa Clara, CA (US);
Russell S. Aoki, Tacoma, WA (US);
Jonathan W. Thibado, Beaverton, OR (US);
Jeffory L. Smalley, East Olympia, WA (US);
David J. Llapitan, Tacoma, WA (US);
Thomas A. Boyd, North Plains, OR (US);
Harvey R. Kofstad, Vrnonia, OR (US);
Dimitrios Ziakas, Hillsboro, OR (US);
Hongfei Yan, Mesa, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.