The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Oct. 12, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Anthony K. Stamper, Burlington, VT (US);

Vibhor Jain, Essex Junction, VT (US);

Renata A. Camillo-Castillo, Williston, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/732 (2006.01); H01L 29/737 (2006.01); H01L 23/482 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 23/4821 (2013.01); H01L 29/41708 (2013.01); H01L 29/66242 (2013.01); H01L 29/66287 (2013.01); H01L 29/732 (2013.01); H01L 29/7378 (2013.01); H01L 23/3171 (2013.01);
Abstract

Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (C). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.


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