The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Apr. 25, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kenji Yoshida, Tokyo, JP;

Hiroki Fujisawa, Tokyo, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40626 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4094 (2013.01); G11C 11/40611 (2013.01); G11C 11/40615 (2013.01); G11C 2211/4061 (2013.01);
Abstract

Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.


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