The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Aug. 04, 2017
United Microelectronics Corp., Hsin-Chu, TW;
Shih-Yin Hsiao, Chiayi County, TW;
Ching-Chung Yang, Hsinchu, TW;
Wen-Fang Lee, Hsinchu, TW;
Nien-Chung Li, Hsinchu, TW;
Chih-Chung Wang, Hsinchu, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.