The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Dec. 20, 2016
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Waseem Kraipak, Kalyani Nagar Pune, IN;

Babji Vallabhaneni, Santa Clara, CA (US);

Vijay Parmar, Santa Clara, CA (US);

Mitrajit Chatterjee, Santa Clara, CA (US);

Assignee:

AMPERE COMPUTING LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/36 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/02 (2013.01); G11C 29/36 (2013.01); G11C 29/4401 (2013.01);
Abstract

An error injection system of a built-in self-repairable memory system renders the redundant spare columns of the repairable memory accessible to built-in self-test (BIST) read and write operations. To this end, the error injection system selectively injects fault data at one or more locations of the main memory during a BIST sequence, causing the BIST controller to issue a repair instruction that allocates one or more spare columns as replacement memory areas for the presumed faulty main memory locations. Thereafter, BIST read/write operations directed to the main memory locations will be performed on the allocated spare columns, thereby allowing the spare columns to be validated as part of the BIST. Injection of fault data to the main memory locations in this manner can also facilitate validation of the built-in self-repair logic by verifying the repair instruction codes that are generated in response to the injected faults.


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