The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Aug. 27, 2014
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Kenta Ninose, Tokyo, JP;

Takuji Itou, Tokyo, JP;

Fumio Yoshioka, Tokyo, JP;

Takashi Tsunehiro, Tokyo, JP;

Go Uehara, Tokyo, JP;

Shigeo Homma, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 11/07 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); G11C 29/765 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01);
Abstract

A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.


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