The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2019
Filed:
Dec. 27, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03F 3/45 (2006.01); H03K 5/24 (2006.01); H03K 3/356 (2006.01); H03K 7/02 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 5/249 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 13/4282 (2013.01); G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); H03K 3/356139 (2013.01); H03K 3/356191 (2013.01); H03K 7/02 (2013.01); G06F 1/324 (2013.01); G06F 2213/0026 (2013.01);
Abstract
Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.