The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Apr. 28, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Hans-Joachim Schulze, Taufkirchen, DE;

Johannes Hacker, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/115 (2006.01); H01L 21/02 (2006.01); H01L 31/18 (2006.01); H01L 31/0352 (2006.01); H01L 31/0288 (2006.01); H01L 31/0224 (2006.01);
U.S. Cl.
CPC ...
H01L 31/115 (2013.01); H01L 31/0288 (2013.01); H01L 31/022408 (2013.01); H01L 31/035272 (2013.01); H01L 31/1804 (2013.01); H01L 31/1864 (2013.01); H01L 31/1872 (2013.01);
Abstract

A method for forming a semiconductor device includes forming an amorphous semiconductor layer adjacent to a lightly doped region of a semiconductor wafer. The lightly doped region forms at least part of a back side of the semiconductor wafer, and the lightly doped region has a first conductivity type. The method further includes incorporating dopants into the amorphous semiconductor layer during or after forming the amorphous semiconductor layer. The method further includes annealing the amorphous semiconductor layer to transform at least a part of the amorphous semiconductor layer into a substantially monocrystalline semiconductor layer and to form a highly doped region in the monocrystalline semiconductor layer at the back side of the semiconductor wafer. The highly doped region has the first conductivity type.


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