The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Feb. 22, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Takashi Terada, Yokkaichi, JP;

Hisashi Kato, Mie, JP;

Noriaki Koyama, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/792 (2006.01); H01L 21/336 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.


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