The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Aug. 04, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Kiyohiko Sakakibara, Yokkaichi, JP;

Satoshi Shimizu, Yokkaichi, JP;

Naoto Norizuki, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 25/065 (2006.01); H05K 7/02 (2006.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01); H01L 27/11568 (2017.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 25/0652 (2013.01); H01L 27/0688 (2013.01); H01L 27/10844 (2013.01); H01L 27/11568 (2013.01); H01L 28/88 (2013.01); H05K 7/023 (2013.01);
Abstract

A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.


Find Patent Forward Citations

Sakakibara, Kiyohiko. (2019). Three-dimensional memory device employing direct source contact and hole current detection and method of making the same (U.S. Patent No. 10199359). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10199359

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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