The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Jul. 28, 2017
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Fredrick B. Jenne, Mountain House, CA (US);

Krishnaswamy Ramkumar, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); H01L 29/51 (2006.01); H01L 29/792 (2006.01); H01L 27/11563 (2017.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28282 (2013.01); G11C 16/04 (2013.01); H01L 21/022 (2013.01); H01L 21/02323 (2013.01); H01L 27/11563 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.


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