The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Feb. 07, 2018
Applicant:

Neo Semiconductor, Inc., San Jose, CA (US);

Inventor:

Fu-Chang Hsu, San Jose, CA (US);

Assignee:

NEO Semiconductor, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 14/00 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 11/419 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0063 (2013.01); G11C 11/005 (2013.01); G11C 11/419 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

A memory device includes a static random-access memory ('SRAM') circuit and a first nonvolatile memory ('NVM') string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.


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