The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

May. 22, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Frank Pueschner, Kelheim, DE;

Alfred Haimerl, Sinzing, DE;

Jens Pohl, Bernhardswald, DE;

Wolfgang Schindler, Regenstauf, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); G06K 19/077 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06K 19/07747 (2013.01); G06K 19/07722 (2013.01); G06K 19/07769 (2013.01); G06K 19/07775 (2013.01); H01L 21/56 (2013.01); H01L 23/49855 (2013.01); H01L 23/49883 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/49109 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01);
Abstract

A smart card module includes a substrate having a first main surface and a second main surface, which is opposite the first main surface. The substrate has a plurality of plated-through holes, which extend through the substrate from the first main surface to the second main surface. The smart card module further includes a chip over the first main surface of the substrate, a first metal structure over the second main surface of the substrate, electrically insulating material, which covers the first metal structure, and a second metal structure over the electrically insulating material, wherein the second metal structure is electrically insulated from the first metal structure by the electrically insulating material. The chip is connected to the first metal structure by at least one first plated-through hole. The chip is connected to the second metal structure by at least one second plated-through hole.


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