The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2019
Filed:
Mar. 02, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Tsair-Chin Lin, San Jose, CA (US);
Jingbo Gao, San Jose, CA (US);
Alon Kfir, San Jose, CA (US);
Long Wang, San Jose, CA (US);
Wei Zeng, San Jose, CA (US);
Zhao Li, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.